The present invention relates to a signal processing circuit, and more particularly, to a signal processing circuit including a timing recovery PLL for matching a clock signal with preamble data signal read from a recording medium and a decision feedback equalizer for reproducing code data recorded on the recording medium based on the clock signal, and to a method for controlling the signal processing circuit.
A decision feedback equalizer (DFE) reproduces data read from a recording medium in accordance with a clock signal generated by a timing recovery PLL. The timing recovery PLL performs a so-called matching operation, in which the output timing of the clock signal is matched with the output timing of the reproduction data from the DFE based on preamble data (matching pattern) recorded on the recording medium.
FIG. 1 is a schematic block diagram showing a prior art signal processing circuit. The signal processing circuit 10 includes an analog-to-digital converter (ADC) 11, a DFE 12, two coefficient registers 13, 14, a PLL phase error detection circuit 15, a timing recovery PLL (TR-PLL) 16, and a control circuit 17.
The ADC 11 samples the analog signal read from the recording medium in accordance with a clock signal CLK generated by the TR-PLL 16 and converts the analog data signal to a digital data signal. The digital data signal is sent to the DFE 12.
The DFE 12 includes a forward (FW) filter 21, an adder 22, a comparator 23, a shift register 24, a feedback (FB) filter 25, an inverter 26, and three switches 27, 28, 29.
The FW filter 21 is connected to the coefficent registers 13, 14 via the first switch 27. A first filter coefficient (start value) used by the FW filter 21 during start-up (i.e., during initiation of the reading operation) is stored in the first coefficient register 13. A second filter coefficient (normal value) used by the FW filter 21 during normal operation (after detection of the preamble data) is stored in the second coefficient register 14. Switching of the first switch 27 selectively sends the filter coefficient of the start value and the filter coefficient of the normal value to the FW filter 21.
The FW filter 21 uses the first filter coefficient to filter the digital data signal from the ADC 11 in accordance with the clock signal CLK during the initial period of the reading operation to generate a signal S1 having a maximum S/N ratio. The FW filter 21 uses the second filter value to perform filtering in the same manner during normal operation to generate the signal S1.
The adder 22 receives the filtered output signal S1 from the FW filter 21 and a feedback signal S2 from the FB filter 25, and adds the output signal S1 and the inverted signal of the feedback signal S2. In other words, the adder 22 functions as a subtractor, subtracting the feedback signal S2 from the output signal S1.
The comparator 23 receives an added signal S3 from the adder 22, compares the voltage of the added signal S3 with a reference voltage REF, and sends a determination signal S4, which is code data (i.e., one or zero) indicating the comparison result, to the shift register 24 via the second switch 28.
The shift register 24 samples the determination signal S4 from the comparator 23 in synchronism with the clock signal CLK and sequentially stores the sampled data. This stores the data, which comprises a plurality of bits, sampled in the past.
The data stored in the shift register 24 is output as a reproduction signal DATA. The data stored in the first bit of the shift register 24 (i.e., the determination signal S4) is the output as a reproduction signal DATA. In this manner, the DFE 12 reproduces code data recorded on the recording medium. The reproduction signal DATA is sent to an external apparatus, such as a microcomputer, after undergoing a data decoding process.
The FB filter 25 receives sampling data from the shift register 24 and eliminates interference between codes that is included in the sampling data. Further, the FB filter 25 outputs the feedback signal S2, which is based on the sampling data, having a plurality of bits and stored in the shift register 24. The feedback signal S2 is sent to the adder 22 via the third switch 29.
The PLL phase error detection circuit 15 receives the added signal S3 from the adder 22 and a signal S6, detects an error or difference between the phase of the read signal and the phase of the clock signal CLK based on the signals S3, S6, and generates a control signal S7 in accordance with the detected error. The signal S6 is either the determination signal S4 of the comparator 23 or the output signal S5 of the inverter 26 which are selected by the switching operation of the second switch 28. The TR-PLL 16 receives the control signal S7 from the PLL phase error detection circuit 15, and matches the phase of the generated clock signal CLK with the phase of the read signal. The shift register 24 is used to perform sampling in accordance with the clock signal CLK from the TR-PLL 16. The sampling is performed at the bit transmission speed of a read signal RD in order to store the determination signal in the shift register 24. The detection signal corresponds to the recorded data on a magnetic disc,
The control circuit 17 receives the reproduction signal DATA from the shift register 24 and controls the switches 27-29 in accordance with the state of the reproduction signal DATA and the number of the bytes read subsequent to the initiation of the reading operation. The preamble data is data in which the pattern of a predetermined number of bits is repeated. A predetermined amount of preamble data is stored on the recording medium. Accordingly, the control circuit 17 controls the switches 27-29 at a predetermined timing based on the amount of preamble data read.
The control circuit 17 performs switch control as described below.
(1) When initiating the reading operation, the control circuit 17 moves the first switch 27 to the first coefficient register 13, the second switch 28 to the comparator 23, and opens the third switch 29. Thus, the FW filter 21 uses the first filter coefficient (start value) from the first coefficient register 13 to shape the waveform of the digital signal from the ADC 11. In this state, the adder 22 sends the output signal S1 of the FW filter 21 to the comparator 23 since the third switch 29 is open. The error detection circuit 15 sends the control signal S7, which is based on the output signal S1 (read signal) from the FW filter 21, to the TR-PLL 16. In this manner, the TR-PLL 16 performs phase matching in accordance with the read signal.
(2) When the control circuit 17 confirms from the reproduction signal DATA that the bit row showing the characteristics of the preamble data (in this case, xe2x80x9c+++xe2x80x9d or xe2x80x9cxe2x88x92xe2x88x92xe2x88x92xe2x80x9d) has been input a predetermined number of times (e.g., three times), the control circuit 17 moves the first switch 27 to the second coefficient register 14, the second switch 28 to the inverter 26, and closes the third switch 29. Here, xe2x80x9c+xe2x80x9d indicates that the voltage of the sampled read signal RD is higher than the reference voltage REF, and xe2x80x9cxe2x88x92xe2x80x9d indicates that the voltage of the sampled read signal RD is lower than the reference voltage REF.
The FW filter 21 shapes the waveform of the digital signal from the ADC 11 using the second filter coefficient (normal value) from the second coefficient register 14. The sampling data stored in the shift register 24 is inverted by the inverter 26. The shift register 24 receives the inverted sampling data via the second switch 28. Accordingly, the shift register 24 repetitively stores the bit row xe2x80x9c+++xe2x88x92xe2x88x92xe2x88x92xe2x80x9d of the preamble data. This initializes the sampling data in the shift register 24 to preamble data.
The adder 22 receives the feedback signal S2 via the third switch 29 from the FB filter 25. That is, the control circuit 17 closes the feedback loop of the DFE 12. Thus, the adder 22 adds the output signal S1, which is derived from the read signal RD and sent from the FW filter 21, with the feedback signal S2 and sends the added signal S3 to the comparator 23 and the error detection circuit 15.
(3) The control circuit 17 counts the byte number of the reproduction signal DATA from the shift register 24 after performing the control described in (2) above, and outputs an enable signal for matching the frequency of the TR-PLL 16 after counting a predetermined number of bytes (e.g., five bytes).
(4) The control circuit 17 counts the byte number of the reproduction signal DATA from the shift register 24 after performing the control described in (3) above, and moves the second switch 28 to the comparator 23 after counting a predetermined number of bytes (e.g., six bytes). In this state, the first switch 27 remains set to the second coefficient register 14, and the third switch 29 remains closed. In this manner, the TR-PLL 16 performs phase matching in accordance with the read signal. The DFE 12 outputs a reproduction signal from which interference between codes is eliminated in accordance with the clock signal CLK.
However, in the above control method, the coefficient of the FW filter 21 must be altered to the data reading second filter coefficient before reading the data that follows the preamble data. This greatly changes the characteristics of the FW filter 21 during the matching operation of the TR-PLL 16. Furthermore, since the FW filter 21 has a multi-stage structure, a relatively long time is required to output the filtered digital signal S1 using the altered coefficient. The signal S1 output by the FW filter 21 during the blank period destabilizes the state of the TR-PLL 16 and may cause a pseudo-lock. Therefore, the operation of the TR-PLL 16 must be stopped from when the first switch 27 is moved to the second register 14 to when the digital signal S1, which is based on the second filter coefficient, is output. This prolongs the matching operation period and hinders shortening of the signal processing time.
Accordingly, it is an object of the present invention to provide a signal processing circuit that prevents pseudo-lock of the timing recovery PLL.
In one aspect of the present invention, a method for controlling a timing recovery PLL is provided. The timing recovery PLL matches the phase of a clock signal with the phase of a preamble data signal. The preamble data signal is part of a read signal corresponding to data read from a recording medium. The method includes the steps of generating a computation read signal by performing a predetermined computation on the read signal, generating a first code data using the computation read signal, comparing the computation read signal and a first reference signal, generating a second code data corresponding to the preamble data signal based on the comparison result, detecting a phase error between the clock signal and the read signal by using the computation read signal and one of the first code data and the second code data, and matching the phase of the clock signal in accordance with the detected phase error.
In another aspect of the present invention, a signal processing circuit is provided. The signal processing circuit includes a decision feedback equalizer for generating a computation read signal by performing a predetermined computation on a read signal read corresponding to data read from a recording medium in accordance with a clock signal. The read signal includes a preamble data signal. The decision feedback equalizer generates first code data by using the computation read signal. The code data generating circuit is connected to the decision feedback equalizer to compare the computation read signal with a first reference signal and generate a second code data based on the comparison result. The second code data corresponds to the preamble data signal. A phase error detection circuit detects the phase error between the clock signal and the read signal using one of the first code data and the second code data. A timing recovery PLL is connected to the phase error detection circuit to generate the clock signal such that the clock signal has a phase matching the phase of the preamble data signal in accordance with the detected phase error.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.